The present invention relates to a technology which is effective when applied to a lithography technique in a method of manufacturing a semiconductor integrated circuit device (or semiconductor device).
In Japanese Unexamined Patent Publication No. Hei 5(1993)-326358 (Patent Document 1), a technology is disclosed in which one negative resist film is exposed to light twice using two masks having respective band-like light shielding portions orthogonal to each other so as to prevent the shape of a corner portion of a contact hole from being rounded.
In Japanese Unexamined Patent Publication No. Hei 9 (1997)-289153 (Patent Document 2), a technology is disclosed in which, in photolithographic processing using a polycide gate electrode and a positive resist in a polycide pattern proximate thereto, one negative resist film is exposed to light twice using two masks having different shielding patterns so as to prevent the shape of a corner portion of the pattern from being rounded.
In Japanese Unexamined Patent Publication No. Hei 11 (1999)-121701 (Patent Document 3), a technology is disclosed in which, in association with photolithography of a Shallow Trench Isolation (STI) region of a NOR-type semiconductor memory device, to avoid an end portion of a rectangular pattern from being rounded due to a proximity effect, a silicon substrate is dry-etched using a hard mask pattern and a line-and-space pattern formed of resist films orthogonal thereto as an etching-resistant mask, and thereby formed with trenches.
In Japanese Unexamined Patent Publication No. 2006-49737 (Patent Document 4) or US Patent Publication No. 2009-122609 (Patent Document 5) corresponding thereto, a technology is disclosed in which, in a flash memory having a split-gate flash memory cell having a Metal Oxide Nitride Oxide Semiconductor (MONOS) structure or a Silicon Oxide Nitride Oxide Silicon (SONOS) structure, write disturb applied to a non-selected memory cell adjacent to a write selected memory cell via a source region is prevented.
In Japanese Unexamined Patent Publication No. 2009-54707 (Patent Document 6) or US Patent Publication No. 2009-050956 (Patent Document 7) corresponding thereto, a technology is disclosed in which, in a flash memory having a split-gate flash memory cell using a MONOS structure or a SONOS structure, disturb resistance during writing in accordance with a Source Side Injection (SSI) method is improved.